T2 - Reliability in advanced Copper/ low k interconnects: Physics and test methodologies

Dr, Girault V., STMicroelectronics, 850 rue Jean Monnet, F38926 CROLLES CEDEX, valerie.girault@st.com

Dr, Girault V., STMicroelectronics, 850 rue Jean Monnet, F38926 CROLLES CEDEX, valerie.girault@st.com

The microelectronic community develops active devices with always higher electrical performances in a minimum of silicon area. However, scaling after scaling, difficulties appeared at different steps. Part of them concerns more and more the interconnects, which must satisfy a low enough resistivity to limit RC delays and a good reliability at very high current densities such as those expected from the ITRS ranging up to 4MA/cm2 at 105°C.

To overreach these difficulties, the microelectronic industry had to deeply re-consider the interconnect architecture technology node after technology nod. One of the choices was to let evolve the dielectric environing the interconnects towards a material with an always lower permittivity, which could decrease the RC delay. On another hand, introducing such a material in the architecture let rise new mechanical and electrical reliability challenges. Similarly, a re-consideration of the interconnect itself in terms of insulating capping layer, metallic diffusion barrier, thermal treatment had to be done to increase the reliability performance and allow such a high current density level.

This tutorial focuses on the reliability methodologies used to describe the performances of the copper interconnects and the low k dielectrics used to build part of the very advanced microelectronic circuits. It will develop in details the 3 main ageing phenomena encountered in these technologies:

• electromigration in copper
• stress induced voiding in interconnects and
• electrical breakdown in Back-End dielectrics

by a review of all the basic and recognized theories and methodologies. A particular attention will be paid on interesting parameters such as the Blech product in electromigration, the mechanical stress free temperature in stress migration, and the question of the lifetime model for dielectric reliability.

Based on the results of the most advanced technologies, expected trends and novel behaviours of reliability parameters with respect to different variables (geometry, interface quality, barrier materials) will be described and explained. In addition, since these observations may lead to the development of new methodologies, these ones will be also presented.

This course will benefit those who are interested in ageing phenomena regarding the copper interconnects and low permittivity dielectrics. This course is open to beginners and some advanced materials should interest Back-End reliability confirmed engineers.

• Introduction to Reliability
• Electromigration (phenomenon, test methodologies, particular observations, advanced solutions)
• Stress Induced Voiding phenomenon (idem)
• Electrical breakdown in Back-End dielectrics (idem)
• Conclusion

Valerie Girault received her Ph.D in 2001 from the National Institute of Applied Sciences in Lyon, France . Her graduate work focused on a memory concept based on mobile protons in silicon dioxide under electric field.

In 2001, she joined the Central R&D Laboratory of STMicroelectronics in Crolles, France , to work as a reliability engineer on advanced copper / low k interconnects. From 2003, she is team leader of the reliability interconnect group in STMicroelectronics CrollesII, in Crolles, France . In particular, these last years were focused on the development of most advanced copper interconnects for 120nm, 90nm and 65nm technologies.