T9 - Design of Experiments (DoE) for reliability and optimization

Jürgen Auersperg (Fraunhofer IZM, Berlin and AMIC GmbH Berlin),

Jürgen Auersperg (Fraunhofer IZM, Berlin and AMIC GmbH Berlin),
Willem van Driel (TU Delft and NXP Semiconductors, NL),
Artur Wymyslowski (Wroclaw University of Technology, PL)

Recent trends in microelectronics and microsystems technology are mainly characterized by miniaturization, increasing levels of technology and function integration. At the same time the business needs are mainly characterized by cost reduction, shorter time to market. As a result, these trends lead to increased chances and consequences of failures, increased design complexity, shorter product development and qualification times and increasing difficulties to meet quality, robustness and reliability requirements.  Presently, trial-error based design methods are still the common practice during new product/process developments, while reliability qualification procedures are still empirical. This situation, however, is becoming the bottleneck for the future development, especially for the advanced Cu/Low-k CMOS and higher level SiP technologies. For competitive product/process developments, it is vital to know and to apply the state-of-the-art of virtual prototyping and qualification based on physics of failure analyses supported Design of Experiments (DoE) and design optimizations.

This workshop will provide advanced knowledge on major failure modes and mechanisms in modern semiconductor approaches, their evaluation by means of non-linear finite element analysis and their occasionally conflicting influence on the overall thermo-mechanical reliability. The relevance of classical failure hypotheses, fracture mechanics of materials and interfaces as well as the fatigue investigation of solder interconnects will be explained in detail and introduced into DoE, Response Surface Methods (RSM), optimization and robust design approaches. Special knowledge will be provided on prototyping algorithms and finally aspects concerning sensitivity and tolerance design. Additionally, all the presented methods would be illustrated by selected example cases of application in microelectronic packaging.

Design, simulation and reliability professionals who are responsible for quality and reliability, prototyping and optimization of electronic assemblies at both the design and manufacturing stage. The course would be also suitable for students and PhD graduates who want to learn how to use and implement the design for optimization methodology.

Survey – Introduction

• Major reliability problems in semiconductors industries
• Status quo of current reliability paradigm
• The state -of-the-art of virtual prototyping and qualification, including the basic theories and methodologies,
• Case study of covering important failure modes related with wafer backend, IC packaging and board level assembly, such as (not limited to):
  Various cracks, and delamination, Wire bonding failures, Solder fatigues, Moisture-induced failures, Warpage
• Challenges and future perspective

FEA-based failure and fatigue evaluation within DoE and optimization

• Major failure modes and classical failure hypotheses,
• Use of fracture mechanics of materials and interfaces,
• Fatigue investigation of solder interconnects,
• Integration of such approaches into DoE and RSM,  in parallel,
  (classical strength hypotheses, solder fatigue, VCCT, Cohesive Zone Method, …)
• Challenges for optimization and robust design applications
• Explanation with the aid of an example.

Introduction to prototyping methods:

• Design of Experiments (DoE),
• Response Surface Modelling (RSM),
• Optimization,
• Finite Element Method (FEM).

Prototyping algorithms

• physical vs. numerical approach,
• sensitivity and tolerance analysis,
• multi-criteria optimization.

Example cases

• QFN and stacked packaging,

Artur Wymyslowski received his M.Sc. degree in 1989, PhD degree in 1994 from the Wroclaw University of Technology, Wroclaw, Poland. Since 1995 he has been employed at Wroclaw University of Technology in the Institute of Microsystem Technology. His research interest is in virtual thermo-mechanical prototyping of component and microsystem packages, application of experimental design methods for optimization of technological processes in electronic devices manufacturing and investigation of electronic materials like lead-free solders and electrically conductive adhesives. He is engaged in teaching FEM modelling of students and dissemination of the results and on-going activities to the outside world. He is a member of IMAPS Poland Chapter and IEEE (CPMT)).

Willem van Driel graduated from mechanical engineering of Technical University of Eindhoven, the Netherlands. He has broad R&D experience covering several multidisciplinary application fields. He is currently a principal scientist at Philips Semiconductors, and also holds an adjunct position in Delft University of Technology, the Netherlands. His scientific interests are Microelectronics and Microsystems technologies, virtual prototyping, virtual reliability qualification and designing for reliability of Microelectronics and Microsystems.
He is member of the organizing committee of the IEEE conference EuroSimE, member of the technical committee of ICEPT, Guest Editor for the IEEE Transactions on Components and Packaging Technologies. He is author and co-author for more than 60 scientific publications, including journal and conference papers, book and invited keynote lectures.

Jürgen Auersperg received his Ph.D. degree in applied mechanics in 1980 from the Chemnitz University of Technology, Germany. He joined the Fraunhofer Institute for Reliability and Microintegration (IZM) as a senior scientist in 1996 and is working in the MicroMaterials Center Berlin. Furthermore, he is responsible for numerical simulations since 1999 at the AMIC company in Berlin.
His specialties are nonlinear finite element simulation, fracture and damage mechanics, fatigue and failure analysis of microelectronics components. His research activities are currently focused on Cu/low-k cracking and delamination issues in BEoL structures. Jürgen Auersperg has given many lectures on fracture and delamination related issues in microelectronics packaging at international workshops and conferences. He has authored and co-authored many technical publications for international journals and conferences.